module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter IDLE = 2'b00;
    parameter FIRST = 2'b01;
    parameter SECOND = 2'b10;
    parameter THIRD = 2'b11;
    
    reg	[1:0]	state;
    reg	[1:0]	next_state;
    
    // State transition logic (combinational)
    always @(state or in[3]) begin
        case(state)
            IDLE:begin
                if(in[3]) begin
                    next_state = FIRST;
                end
                else begin
                    next_state = IDLE;
                end
            end
            FIRST:begin
                next_state = SECOND;
            end
            SECOND:begin
                next_state = THIRD;
            end
            THIRD:begin
                if(in[3]) begin
                    next_state = FIRST;
                end
                else begin
                    next_state = IDLE;
                end
            end
        endcase
    end
    
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset) begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    // Output logic
    assign done = (state == THIRD);

endmodule
